The digital processor of this sort includes, for instance, a radio communication device such as a cellular phone, a waveform analyzer, a frequency synthesizer and the like. The frequency synthesizer includes a device to which a phase locked loop (PLL) shown in FIG. 18 is applied, and further includes a phase comparison function configured with a programmable logic device (PLD). In this drawing, the PLL works such that it divides an oscillation output of a voltage controlled oscillator 101 into 1/N with a divider 102, inputs the divided output into one input terminal of a phase comparator 103, and at the same time, divides an oscillation output 104 of, for instance, a crystal oscillator 104 being a reference signal generator into 1/M with a divider 100, inputs the divided output into the other input terminal of the phase comparator 103, and feeds back the compared signal to the voltage controlled oscillator 101 via a loop filter 105. When this PLL is locked, a frequency fvco of the oscillation output of the voltage controlled oscillator 101 and a frequency f0 of the oscillation output of the quartz oscillator 104 become fvco=(N/M) f0, because there is a relation of fvco/N=f0/M. Since the divider 102 is configured with a programmable counter, and is able to set a frequency divider ratio N with digital data from outside, it becomes possible to set the frequency of the fvco without restraint. The frequency synthesizer is able to switch an output frequency of the voltage controlled oscillator 101 in a wide frequency range in steps of 1 MHz or the like by changing the frequency divider ratios of the dividers 100 and 102 with an outside circuit, and further, by forming the PLL in a multiple configuration.
In the frequency synthesizer taking the above PLL system, when a phase comparison function of the phase comparator 103 is conducted in a digital processing, the oscillation output of the voltage controlled oscillator 101 is converted into a digital signal at the A/D converter, the digital signal and the oscillation output (clock signal) of the quartz oscillator 104 are captured into a digital processing circuit to perform a phase comparison processing, and the comparison result is restored to an analog signal at a D/A converter to be a voltage controlled signal of the voltage controlled oscillator 101.
However, a spurious noise appears in the above-described frequency synthesizer, which results in performance deterioration of the device. The reason for this is considered that a large holding current and a small holding current in the A/D converter are repeated at a certain cycle, which is responsible to this deterioration.
Meanwhile, in Patent Document 1, there is a description that M-series pseudo-random numbers uncorrelated to each other are generated, and digitally added. Then, they are subjected to D/A conversion, and analogously added to an analog input signal to be an input of the A/D converter. However, since a band noise generator is not used, a considerably large output level is generated even within an output frequency of the A/D converter. The circuit is used in the device, and if it is used for restraint of spurious generation with the advance of charge/discharge of the holding current of the A/D converter, it affects the signal processing at the subsequent stage.
Patent Document 1:
Japanese Patent Application Laid-open No. Hei 6-132825